digital multi - p hase gpu buck controller chl8266 october 12 , 2011 | final | v1. 05 1 features ? gpu - compliant digital pwm controller ? programmable 1 - phase to 6 - phase operation ? configurable switching frequency from 200 khz to 1mhz per phase with accuracy better than 2% ? ir dynamic phase control ? 1 - phase to 2 - phase psi for light loads ? adaptive transient algorithm minimizes output bulk capacitors ? enables thermal phase balancing ? smbus interface for configuring and monitoring ? compatible with ir atl drivers and tri - state driv ers ? nine bytes of nvm storage available for customer use ? +3.3v supply voltage; 0oc to 85oc ambient operation ? rohs compliant, msl level 1 package applications ? high performance gpu voltage regulation solutions ? high current and high - efficiency applications basic application figure 1: chl8266 basic application circuit description the chl8266 is a 6 - phase digital synchronous buck controller for regulation of high - performance gpu platforms. the chl8266 output vid table is fully compliant with vr11.1 specifications. the chl8266 deploys a number of efficiency shaping features. psi can be programmed to be up to four phases for optimum light - load efficiency, and the controller can autonomously add/drop phases from mid to high and back to mid current ranges to deliver 90+% efficiency across the entire load range. irs unique adaptive transient algorithm, based on non - linear digital pwm algorithms, minimizes output bulk capacitors. chl8266 supports ntc temperature sense to report temperature and trigger vr hot and otp faults. digital thermal balancing allows proportional current imbalance between phases. the chl8266 provides extensive ovp, uvp, ocp and otp fault protection. device and fault configuration parameters are easily defined using the ir digital power design center ( dpdc ) gui and stored in on - chip non - volatile memory (nvm). the 2 - pin smbus interface can be used to monitor a variety of operating parameters on chl8266 based vrs. the chl8266 truly simplifies vrd design and enables fastest time - to - market with its set - and - forget methodology . pin diagram figure 2 : chl8266 package top view p w m 1 1 2 v v _ g p u i s e n 1 i r t n 1 3 . 3 v s v _ d i o e n a b l e e n a b l e s v _ c l k c h l 8 2 6 6 v r _ r d y v r _ h o t # p w m 2 i s e n 2 i r t n 2 p w m 4 i s e n 4 i r t n 4 p o w e r s t a g e 5 . . . v c c p w m 1 _ l 2 i s e n 1 _ l 2 i r t n 1 _ l 2 p o w e r s t a g e 2 p o w e r s t a g e 1 v r _ r d y v r _ h o t # s d a s c l p o w e r s t a g e 6 s d a p w m 5 i s e n 6 e n v r t n r c s m p s i # i s e n 5 i s e n 4 i s e n 3 p w m 6 t p 3 v i d 1 v i d 2 v i d 3 v i d 4 v i d 5 t p 4 t p 5 v g p u v c c s c l p w m 4 t p 2 v r _ r e a d y i r t n 3 i r t n 4 i r t n 6 i r t n 5 r c s p t s e n v r _ h o t p w m 3 v i n s e n t p 1 v 1 8 a r r e s n c v c c 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 4 8 4 7 4 6 4 5 2 4 2 5 2 6 2 7 2 8 1 7 1 8 1 9 2 0 2 1 2 2 2 3 4 0 3 9 3 8 3 7 3 6 3 5 4 1 4 2 i s e n 2 i s e n 1 i r t n 1 i r t n 2 p w m 2 p w m 1 n c 1 5 1 6 4 4 4 3 v c c 3 3 3 2 3 1 3 0 2 9 3 4 g n d s a d d r c h l 8 2 6 6 t o p v i e w 4 8 p i n 7 m m x 7 m m q f n
digital multi - p hase gpu buck controller chl8266 october 12 , 2011 | final | v1. 05 2 ordering information chl8 266 - ? ? ? ? ? package tape & reel qty part number qfn 3000 chl8266 - crt qfn 3000 chl8266 - xx crt 1 notes: 1 . xx indicates c ustomer s pecific c onfiguration f ile . figure 3: chl8266 top view enlarged t C tape and reel r C package type (dfn) c C operating temperature (commercial standard) xx C configuration file id s d a p w m 5 i s e n 6 e n v r t n r c s m p s i # i s e n 5 i s e n 4 i s e n 3 p w m 6 t p 3 v i d 1 v i d 2 v i d 3 v i d 4 v i d 5 t p 4 t p 5 v g p u v c c s c l p w m 4 t p 2 v r _ r e a d y i r t n 3 i r t n 4 i r t n 6 i r t n 5 r c s p t s e n v r _ h o t p w m 3 v i n s e n t p 1 v 1 8 a r r e s n c v c c 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 4 8 4 7 4 6 4 5 2 4 2 5 2 6 2 7 2 8 1 7 1 8 1 9 2 0 2 1 2 2 2 3 4 0 3 9 3 8 3 7 3 6 3 5 4 1 4 2 i s e n 2 i s e n 1 i r t n 1 i r t n 2 p w m 2 p w m 1 n c 1 5 1 6 4 4 4 3 v c c 3 3 3 2 3 1 3 0 2 9 3 4 g n d s a d d r c h l 8 2 6 6 t o p v i e w 4 8 p i n 7 m m x 7 m m q f n
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